The present invention is related to the field of bus design for integrated circuits and, more particularly, to the design of scan compatible bus control circuitry.
A bus is a plurality of signal lines which moves several bits in parallel from one location to another in an integrated circuit. Data buses in present day microprocessors, for example, are typically 16 or 32 bits wide. That is, the bus has 16 or 32 signal lines which carry 16 or 32 data bits at time in parallel. To place the bits on the bus, each signal line has one or more driver circuits which can pull the voltage on the signal line high for a logic 1, or low for a logic 0. Often, more than one driver circuit is attached to a bus signal line so that different functional units on an integrated circuit may use the same bus. Of course, one and only one driver should drive a bus signal line at any one time. Besides the problem of the determining the logic level of the bus signal, two or more simultaneously active drivers cause excessive currents when the data of the two drivers differ, i.e., one driver is at the logic 1 state and the other driver is at the logic 0 state. Thus the drivers of a bus are operated so that only one set of drivers is enabled at a time; the other sets of drivers are disabled.
It is desirable that the elements of an integrated circuit be tested to check their functional operation. For a bus, it is desirable to check the bus itself, the bus drivers, and the control circuitry of the bus drivers. In testing an electronic system, including integrated circuits, test bits which are scanned into the system provide an efficient testing method. The test bits are typically created by an automatic test pattern generator. A problem in testing the bus, its drivers and control circuitry with the test bits of an automatic test pattern generator is the "one, and only one" driver condition. Two or more simultaneously active drivers cause excessive currents when the data of the two drivers differ, i.e., one driver is at the logic 1 state and the other driver is at the logic 0 state. On the other hand, if there are no active drivers, this allows the bus to float which may also cause excessive current. Heretofore, previous designs have not adequately handled the combination of scanning and the three-state control of a bus and its drivers.
On the other hand, the present invention solves or substantially mitigates this problem. Furthermore, the present invention allows for the control of the bus and its drivers with precise timing to avoid undesirable bus contention at high speed.